// Test file for ifdef processing - in general all defines
// starting with D should eval true, those starting with U should be false
// Run with:
// +define+D99 +define+D98=XXX
//
`ifdef D99 // this is defined on the command line
`ifdef D98 // this too
module test;
`define D01 TEST // this should get done
`else
`define U01
`endif
`endif
`define U02 TEST /* comment */
`ifdef U02
reg test1; /* this should be true here */
`endif
`undef U02
`ifdef D01
`ifdef U01
reg testX;
`else
reg test2; // this is the correct one
`endif
`ifdef U02
reg testY;
`endif
`endif
`ifdef FOR_WEB_PAGE
`include "inc1.v"
`else
`include "../preproc/includes/inc1.v"
`endif
`ifdef D11
`ifdef D12
`ifdef D13
`ifdef D14
reg testZ; // actually this isn't defined yet
reg testZ; // actually this isn't defined yet
reg testZ; // actually this isn't defined yet
reg testZ; // actually this isn't defined yet
`else
reg test3; // so this should be true
`endif
`endif
`endif
`endif
`define D02 THIS CONTROLS THE BEHAVIOUR OF inc1.v
`include "inc1.v"
`ifdef D11
`ifdef D12
`ifdef D13
`ifdef D14
reg test4; // now this should be true
`else
reg testA;
`include "inc2.v" // this shouldn't get included
`undef D31 // and this should be undefined
`endif
`ifdef U21 // check inc 2 wasn't included
reg testB;
`endif
`endif
`endif
`endif
// test the file inc3.v was read
`ifdef D31
`ifdef U31
reg this_is_false;
`else
`ifdef D32
`ifdef D33
`ifdef U32
reg this_is_false;
`endif
`ifdef U32
`else
reg this_is_true;
`endif
`else
`endif
`endif
reg this_is_true2;
`undef D01
`endif
`else
reg this_is_false;
`endif
`ifdef D01 // this time it should be undefined
`else
endmodule
`endif
This page: |
Maintained by: |
v2html730@burbleland.com |
|
Created: | Thu Jan 15 16:17:01 2009 |
|
From: |
testing/preproc/verilog/std_pre_proc.v |