/* -*-Verilog-*-
*******************************************************************************
*
* File:         count_to_x.v
* RCS:          $Header: $
* Description:  Count to X!
* Author:       Costas Calamvokis
* Language:     Verilog
* Package:      N/A
* Status:       Experimental (Do Not Distribute)
*
* Copyright (c) 1998 Costas Calamvokis, all rights reserved.
*
*******************************************************************************
*/


module count_to_x(
    clk,
    reset,
    enable,
    out);

parameter X=0;      // Note it doesn't actually get to X: it
                    //    counts 0,1,2...X-1,0,1..
parameter WIDTH=0;

input clk;
input reset;
input enable;
output [WIDTH-1:0] out;
reg    [WIDTH-1:0] out;


always @(posedge clk)
    begin
    if (reset) 
        begin
        out = 0;
        end
    else if (enable)
        begin
        if (out == (X-1))
            begin
            out = 0;
            end
        else
            begin
            out = out + 1;
            end
        end
    end

endmodule

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