/* -*-Verilog-*- ******************************************************************************* * * File: top.v * RCS: $Header: $ * Description: The top of the millennium clock * this idea could make me a millon if I just got round to * mass producing it soon * Author: Costas Calamvokis * Language: Verilog * Package: N/A * Status: Experimental (Do Not Distribute) * * Copyright (c) 1998 Costas Calamvokis, all rights reserved. * ******************************************************************************* */ //*** click on defs.v to jump to that file `include "defs.v" module top ( clk, // 32.768 kHz clock reset, // should be held high for one cycle at 00:00:00 1/1/0000 seg_a, // seven segment display: seg_b, // seg_c, // +-a-+ seg_d, // f b seg_e, // |-g-| seg_f, // e c seg_g // +-d-+ ); input clk; input reset; output seg_a; output seg_b; output seg_c; output seg_d; output seg_e; output seg_f; output seg_g; `ifdef THE_HARD_WAY wire [3:0] millennium; initial //*** Click on `OSC_FREQ to jump to where this is defined (in defs.v) //*** (if you are using frames it will appear in the bottom frame) $display("Oscillator frequency is %d", `OSC_F); //*** click on count_millennia to go to the module count_millennia m1 ( .clk(clk), .reset(reset), .millennium(millennium) ); //*** click on decode to go to the module decode d1 ( .bcd_input(millennium), .seven_seg_output({seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g}) ); `else //*** This code will appear greyed out if this file was processed //*** with +define THE_HARD_WAY reg seg_a; reg seg_b; reg seg_c; reg seg_d; reg seg_e; reg seg_f; reg seg_g; reg [49:0] count; reg [3:0] millennium; always @(posedge clk) begin if (reset) begin count <= 50'd0; millennium <= 4'd0; end else begin if (count == 50'd1033371647999999) begin count <= 50'd0; millennium <= millennium + 4'd1; end else begin count <= count + 1; end end end always @(millennium) begin case (millennium) // synopsys full_case parallel_case 0: {seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g} = 7'b1111110; 1: {seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g} = 7'b0110000; 2: {seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g} = 7'b1101101; // the warranty will have expired long before this happens default: {seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g} = 7'b1101101; endcase end `endif endmodule /* * Click on this link to go back to v2html home page: * http:../../../v2html.html */