/* -*-Verilog-*-
*******************************************************************************
*
* File:         divide_by_365.v
* RCS:          $Header: $
* Description:  
* Author:       Costas Calamvokis
* Language:     Verilog
* Package:      N/A
* Status:       Experimental (Do Not Distribute)
*
* Copyright (c) 1998 Costas Calamvokis, all rights reserved.
*
*******************************************************************************
*/



module divide_by_365 ( clk, reset, enable, out);
`include "defs.v"

input clk;
input reset;
input enable;
output out;

reg [8:0] count;

wire  [8:0] new_count = count + 1;

assign out = last_count(count);

always @(posedge clk)
    begin
    if (reset)
        begin
        count = 0;
        end
    else if (enable)
        begin
        if ( out )
            count = 0;
        else
            count = new_count;
        end
    end


function last_count;
    input [8:0] count;
    begin
    last_count = (count == (`DAYS_IN_YEAR - 1))
    end
endfunction



endmodule

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