/* -*-Verilog-*-
*******************************************************************************
*
* File:         pulse_per_year.v
* RCS:          $Header: $
* Description:  
* Author:       Costas Calamvokis
* Language:     Verilog
* Package:      N/A
* Status:       Experimental (Do Not Distribute)
*
* Copyright (c) 1998 Costas Calamvokis, all rights reserved.
*
*******************************************************************************
*/


module pulse_per_year ( clk, reset, out);

input  clk;
input  reset;
output out;


divide_by_32768 d1( .clk(clk), .reset(reset), .enable(1'b1), .out(sec));

divide_by_60 d2(
    .clk(clk),
    .reset(reset),
    .enable(sec),
    .out(min));

divide_by_60 d3(
    .clk(clk),
    .reset(reset),
    .enable(min),
    .out(hr));

divide_by_24 d4(
    .clk(clk),
    .reset(reset),
    .enable(hr),
    .out(day));

divide_by_365 d5(
    .clk(clk),
    .reset(reset),
    .enable(day),
    .out(out));

endmodule

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