module top (a,b);

output b;
input  a;

sub1 s1(
    .c(a),
    .d(b));  // click on .d to go down

endmodule
























































This page: Maintained by: v2html730@burbleland.com
Created:Thu Jan 15 16:17:00 2009
From: testing/sig_down/verilog/down1.v

Verilog converted to html by v2html 7.30.1.3 (written by Costas Calamvokis).Help