// Signal Tracing example
// Imagine you want to know what drives b
// Start at step 1 ----+
// |
// V
module top (a,b);
output b; // 1) click on b to see what drives it
// once you've clicked follow the instructions
// at the top to the window
input a; // 9) finally a is an input
sub1 s1(
.c(a), // 8) now we're back here, click on a
.d(b)); // 2) b is driven by output d of sub1, so...
// click on .d to see what drives this output
// (only outputs can be clicked on in instantiations)
endmodule
module sub1 (c,d);
input c; // 7) c is an input, click on it to see what drives it
output d;
sub2 s1(
.e(c), // 6) e is driven by c , click on c to see what
// drives it
.f(d)); // 3) output d of sub1 is driven by output f of sub2
// click on .f to see what drives output f
endmodule
module sub2 (e,f);
input e; // 5) e is an input to the module. As the module
// is only instantiated once you can click on
// e to go up to the line that drives e
output f;
always @(e)
begin
f = !e; // 4) Output f is driven by !e.
end // As e is on the right hand side of the expression
// you can click on e to find out what drives it.
endmodule
This page: |
Maintained by: |
v2html730@burbleland.com |
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Created: | Thu Jan 15 16:17:00 2009 |
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From: |
testing/sig_trace/verilog/trace_example.v |