testing/sig_up_and_down/verilog/up_and


module top (a,b);

input  a;
output b;

sub1 s1(
    .c(a),
    .d(e));     // click on .d to see what drives it

sub2 s2(
    .c(e),      // click on e to see what drives it
    .d(b)); 

endmodule

This page:	Maintained by:	v2html730@burbleland.com
	Created:	Thu Jan 15 16:17:00 2009
	From:	testing/sig_up_and_down/verilog/up_and_down1.v

Verilog converted to html by v2html 7.30.1.3 (written by Costas Calamvokis).

Help