[Up: top s2]
module sub2 (c,d);

input  c;      // click on c to see what drives the input
output d;

assign d = ~c; // click in c to see what drives it

endmodule
























































This page: Maintained by: v2html730@burbleland.com
Created:Thu Jan 15 16:17:01 2009
From: testing/sig_up_and_down/verilog/up_and_down3.v

Verilog converted to html by v2html 7.30.1.3 (written by Costas Calamvokis).Help