v2html 6.0 quick help |
Your page was generated using an old version of v2html - for the latest version visit the v2html home page. |
Linking in verilog code | ||
Click on | Example | To go to |
Instance | sub_mod u1 (...); | Submodule definition (down hierarchy) |
Arrow above module line | module ... |
Module instantiation (up hierarchy) |
Place task/function is used | r = my_func(); | Task/function definition |
Place define is used | `MY_DEF | Place define is defined |
Included file | `include "my_file.v" | Included file |
Instance output port | sub_mod u1(.out1(signal1),...) | Place where signal is driven in submodule |
Input definition | input in_a; | To instantiation port line (when instantiated only once) |
Place parameter is used | new_state <= state_0; | Parameter definition |
Index mark after module or signal definition | module my_mod ( | Module or signal in index |
Hierarchy Page | |
Click on | To go to |
Module name | Module source code |
Task name | Task source code |
Function name | Function source code |
Index mark after name | Name in index |
Collapsible hierarchy page | |
Click on | To... |
[Hide All] | Hide all the hierarchy |
[Show All] | Show all levels of the hierarchy |
Show a level of hierarchy | |
Hide all levels of hierarchy below |
Frames | |
Frame | Shows |
Top | Hierarchy |
Middle | Verilog code |
Bottom | Values of defines and parameters |
Default colours | |||||||
comment | compiler | define | function | keyword | module | parameter | port |
ifdefed out | string | systemtask | task | signal inout | signal inout_reg | signal input | signal integer |
signal output | signal output_reg | signal real | signal reg | signal supply0 | signal supply1 | signal time | signal tri |
signal tri0 | signal tri1 | signal triand | signal trireg | signal wand | signal wire | signal wor |
Tips |
|
© 1999 Costas Calamvokis |