| v2html 6.0 quick help |
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| Linking in verilog code | ||
| Click on | Example | To go to |
| Instance | sub_mod u1 (...); | Submodule definition (down hierarchy) |
| Arrow above module line | module ... |
Module instantiation (up hierarchy) |
| Place task/function is used | r = my_func(); | Task/function definition |
| Place define is used | `MY_DEF | Place define is defined |
| Included file | `include "my_file.v" | Included file |
| Instance output port | sub_mod u1(.out1(signal1),...) | Place where signal is driven in submodule |
| Input definition | input in_a; | To instantiation port line (when instantiated only once) |
| Place parameter is used | new_state <= state_0; | Parameter definition |
| Index mark after module or signal definition | module my_mod |
Module or signal in index |
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Hierarchy Page
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| Click on | To go to |
| Module name | Module source code |
| Task name | Task source code |
| Function name | Function source code |
| Index mark after name | Name in index |
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Collapsible hierarchy page
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| Click on | To... |
| [Hide All] | Hide all the hierarchy |
| [Show All] | Show all levels of the hierarchy |
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Show a level of hierarchy |
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Hide all levels of hierarchy below |
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Frames
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| Frame | Shows |
| Top | Hierarchy |
| Middle | Verilog code |
| Bottom | Values of defines and parameters |
| Default colours | |||||||
| comment | compiler | define | function | keyword | module | parameter | port |
| ifdefed out | string | systemtask | task | signal inout | signal inout_reg | signal input | signal integer |
| signal output | signal output_reg | signal real | signal reg | signal supply0 | signal supply1 | signal time | signal tri |
| signal tri0 | signal tri1 | signal triand | signal trireg | signal wand | signal wire | signal wor | |
| Tips |
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| © 1999 Costas Calamvokis |