The Rough Verilog Parser

The Rough Verilog Parser is a perl module that makes it easy to extract information from verilog designs. For instance, to print a list of all the modules in a set of verilog filse you could write a script like this:

#!/usr/bin/perl -w
use rvp;   # use the rough verilog parser

# Read in all the files specified on the command line
$vdb = rvp->read_verilog(\@ARGV,[],{},1,[],[],'');

# Print out all the modules found
foreach $module ($vdb->get_modules()) { 
	print "$module\n"; 

Other things that it can do are:

It does all this in a comment and whitespace insensitive way, and it understands verilog, so it won't be confused by stuff like this.

Here are the links to save to get the Rough Verilog Parser:

In order to use this perl module you need to put it somewhere perl can find it. You can put it:

If you send me your rvp scrips I'll add them into my regression tests, so I can make sure I don't break them when I change things. Also if you like, I can put them up here so other people can use them.

So far one person offered a script to be put here:

Changes in 7.61

There are no important changes, just one small change I had to make to get v2html 7.30 to work with the newer rvp.

Changes in 7.60

Note: the function get_define behaviour has changed for command line defines. It used to return an empty list, but it now returns ("",0,value).

New features:

Fixed Bugs:

Changes in 7.30

New features:

Support for language constructs I missed in 7.0:

Bugs fixed:

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© 1999-2009 Costas Calamvokis