The Verilog to html converter
What's new in 18.104.22.168
This is the same as 7.30, but which uses the newer RVP 7.61. I am rather embarrassed that I have not put this up sooner!
What's new in 7.30New features:
- Multiple defines are now handled correctly (linked to the correct place). get_define can now take a file and line as arguments.
- New experimental RVP functions get_current_instantiations_parameters and get_modules_parameters.
- RVP now parsers about 50% faster.
- Signals local to a block are now ignored (instead of giving parse errors).
- Instance lists.
- Functions returning time/realtime.
- Continuation lines in defines.
- Hierarchical identifiers.
- ifdef and endif on same line.
- multiple dirs with +incdir+...+...+...
- Single instance parameter without brackets - illegal but accepted by other tools (prints a warning).
- warn about registers that are also inputs.
- Parameters in tasks and functions.
- Signal drive strength and charge strength.
- First character of signal driving a port got cut off.
- Command file ending in single line comment with no new-line.
- Delay values didn't accept decimals.
- Port con capturing was unreliable.
- // with no newline at end of file.
- Infinite loop with $ in define name.
- Relative file names in includes now are treated as relative to the included file, not the execution directory as they were in 7.0.
- Multiple Brackets in named ports bug.
- default in signal name in case statement bug.
- UDPs without names being skipped.
- Problems with signal popup in Mozilla 1.0 and Netscape 7.0.
- File names with spaces.
- Problems when a directory name matched a module name.
What's new in 7.0The main new features are:
- Support for Verilog 2001 (IEEE 1364-2001) for more details see my verilog 2001 page.
- Support for Netscape 6.x (code generated by earlier versions of v2html does not work at all in Netscape 6.x - they changed a bunch of stuff!).
- Included files are handled properly. The include file is read at the time the `include is found, so that includes can appear anywhere and the code will be correctly linked.
- Improved running on Windows platforms (tested with Active State Perl on Windoze 98).
- Completely new parsing code (needed for the Verilog 2001 and include
file changes) also has the advantages that it:
- does not get confused by escaped identifiers containing semicolons, brackets and equal signs.
- correctly handles defines, maintaining their values across file boundaries (so the -g global defines option is gone).
- always expands defines (this doesn't slow it down anymore, so the -exp option is gone).
- does not get confused by escaped quotes in strings.
- handles tasks and functions that only contain one statement.
- Parser Warnings are saved up and printed right at the end to make seeing them easier. Unresolved modules and undefined defines are also reported.
- New more soothing appearance.
- Nicer buttons (NS 6.0, IE 4.0 or later) to access the indexes. Can be clicked anywhere.
- First release from Portugal!
- Signals driven in tasks now found correctly.
- /* */ comments allowed in command files.
- reg allowed before declaration before output declaration.
- duplicates in Cascading Style Sheet classes
- too much whitespace at end of files.
- includes in cases hanging (the new parser now parses this code correctly).
- absolute paths in includes.
- a lot more funnies in the old parser have gone away.
- does not print warnings during parsing, any warnings are stored and can be retrieved afterwards with a new get_problems function. What you do with these warnings is up to you, for instance you could choose to die if you get "Confused" warnings, but accept "unresolved module" warnings (see any of the example scripts for examples of using this.
- get_module_signal and get_signal_by_context return extra a_file and i_file
- fixed rvp example: synth_make.pl which didn't get updated when I changed get_modules_file to return an array
- get_inst_by_context gone, replaced by get_inst_on_line
- range returned by get_module_signal no longer contains [ and ]
- the global_include (third argument to read_verilog) and exp (last argument) are now ignored because include files are handled correctly and defines are always expanded.
What's new in 6.0Major improvements are the signal popup window and much better support of Internet Explorer 4.0 and 5.0.
- New signal popup window which makes following signals much easier. It also lets you trace back to the source of a signal with one click (find source). This feature works with Netscape Navigator 4.x and Internet Explorer 4.0 and 5.0.
- New vertical frames option (-VF) puts the hierarchy down the side of the window. Thanks to Alex Driker for suggesting this (and many other things that I haven't had time to do yet!).
- Added highlighting of the signal after a search using the signal popup window - this only works with Internet Explorer, Netscape doesn't have this capability.
- Fiddled with the TABLE.NB sections of the Cascading Style Sheet to stop the navigation buttons all merging together in Internet Explorer. Also, old versions of the Cascading Style Sheet are now overwritten unless they have been editted to allow smoother upgrades.
- Fixed warnings on Perl 5.005.
- Fixed bug with escaped signalnames with square brackets in them (like \sig).
- Fixed a bug which meant that multipage signals, files and modules indexes were not being linked correctly. Thanks to Arnon Sharlin for reporting this one.
- Moved all www.abrizio.com links to point at v2html's new home at www.burbleland.com.
- Added blank space to the bottom of each file to make the scrolling work better for stuff near the bottom - thanks to Richard Moore for suggesting this at an opportune time.
What's new in 5.6The biggest changes are the new -exp option and the huge speed improvements. Here's a complete list:
- Defines can now be expanded before parsing using the new
-exp option. This is most useful if you define verilog
keywords or module names, for instance doing things like:
`define O output `define I input `define MM my_module module `MM ( a , b , c ); `0 a; `I b,c;used to confuse the parser. Now running with -exp the module, outputs and inputs will be found correctly. Note that the resulting html will still include the defines unexpanded, but because the parser used the expanded version my_module will appear in the hierarchy and a, b and c will be recognized correctly as outputs and inputs.
Many thanks to Rajeev Jayavant who wrote a version of this code that convinced me that it wouldn't be a hard thing to add, and later tracked down a problem with `resetall that adding this feature exposed.
- Huge speed improvement! I finally ran a profiler on the code and
was amazed by what I found! The speed improvement depends on the
verilog code, the biggest gains are on gate level netlists. For
instance, a 45,000 line gate level netlist took 45 minutes to process
using 5.0, whereas with 5.6 it only takes 3 minutes.
Thanks to all those that wrote in complaining about the speed including Tom Jones who's mail finally inspired me to run the profiler.
- Fixed a bug: -htf didn't work unless -js was used.
- `resetall now doesn't reset all the defines to match the behaviour of VCS and Verilog-XL.
- RVP: read_verilog has a new expand defines argument which when set causes defines to be expanded before parsing.
- RVP: get_files_includes now returns file names even if rvp can't find the file.
What's new in 5.0Here are the major changes:
- The biggest change is that the appearance everything is now controlled by
cascading style sheets. This means that:
- The code looks very dull in old browsers that don't support cascading style sheets (such as Netscape Navigator 3.0).
- Different links are now different colours, so you can tell an input from an output from a registered output just by the colour.
- By default links are now underlined because you can't tell a link by the colour.
- Customization using the -font command line option is no longer supported. Instead you can edit the cascading style sheet to get the appearance you want (v2html will write a default one if there isn't one in the output directory, but after that it won't overwrite it). Cascading style sheets are much more powerful than the old -font options - you can change the colour, background, font type, font size and a number of other properties. So, if you want all your comments to flash pink in 24 point helvetica bold italics on a purple background just run v2html once and edit the v2html.css file produced!
- Instances that don't use the .port_name( ) syntax are now handled. This is the
most requested feature and I finally got round to doing it! So now you can
convert that old code that just says:
mod m1(a,b,c);and v2html will figure out what ports they are connected to.
- Big designs are now handled better (in 4.0 some of the html files were so big
that they either took too long to load or, worse, caused your browser to
- Large files are split across multiple html pages (by default every 1000 lines but this can be changed with the new -lines option. A new navigational bar appears at the top of these files so that you can browse around the pages. Of course all the links are still to the correct places.
- Large indexes are now split across multiple pages.
- Quick Search now works across multiple pages. Middle click on a link and it searches forwards, loading up the next page if the text is not found in the current file.
- Better support for VCS/verilog options allowing you to run v2html using the same
command file that you use for simulation:
- multiple library extensions using +libext+EXT1+EXT2+EXT3 or multiple +libext+EXT options.
- verilog -v option now supported.
- Most VCS/verilog command line options that v2html doesn't understand are now ignored.
- All +args that v2html doesn't understand are also ignored.
- Quick search is now more robust and on by default (turn it off with the new -nqs
you click on a link before it has finished drawing!). It also remembers the
state you had it in last time you looked at it (using cookies).
- Tasks and functions are now handled properly in the collapsible hierarchies.
- Primitive modules and macromodules are now handled and linked just like regular
- Improved incremental mode (-i) deletes the files that it produced last time (to stop junk building up in the output directory) and detects changes to the options used.
What's new in 4.0New features (a short list that hides a lot of code!):
- Indexes! v2html now produces indexes of all the modules, signals, tasks, functions and files in your design. These indexes are arrange alphabetically and contain loads of information. Here is an example.
- +incdir -y +libext flags that work like verilog's telling v2html where to search for files to convert.
- Includes are now handled better (particularly if modules are instantiated in the included files).
- RVP: signals that are used in always @(posedge ) and always @(negedge ) are tagged. This information is propagated up the hierarchy to connected signals and can be accessed with get_module_signal.
- RVP: new get_files_fullpath and get_files_includes functions.
- RVP: a new example of a script that generates a makefile for synthesis using plenty of RVP functions (including the two new ones above).
- RVP: You can also specify a list of include directories, library directories and a library extension to the read_verilog_function.
- Spelling mistake of primitive.
- Square brackets in escaped identifiers.
What's new in 3.5New features:
- -tab option allows you to specify a non-standard tab spacing.
- -qs option turns on quick search allows you to click on a link and scroll to the next or previous occurrence in that file (only works in Netscape 4). This should be useful for finding where a signal is next used for instance.
- New "Quick help" at the bottom of each page.
- Parameters are now linked to their definitions.
- HTML generation should now be faster.
- `defines in comments gave parse errors.
- RVP: port connections had an extra ) on them.
© 1999-2009 Costas Calamvokis